Level 2 · M.Sc

Theory & Applied Hardware

Syllabus · 42 phases · ~1 year

Every unit this programme teaches, in the order it is taught. Headlines only — the material itself opens once you are enrolled.

Dates, price and prerequisites

Phase 0 Foundations & tooling
Phase 1 The HDL & Methodology
Phase 2 Semiconductors & the diode
Phase 3 The MOSFET as a switch
Phase 4 CMOS logic
Phase 5 Boolean algebra & truth tables
Phase 6 Universal gates: everything from NAND
Phase 7 Multiplexers, decoders & encoders
Phase 8 Adders & subtraction
Phase 9 The ALU & Karnaugh-map minimization
Phase 10 Latches & the bistable element
Phase 11 Flip-flops & clocks
Phase 12 Registers, shift registers & counters
Phase 13 Finite-state machines & timing
Phase 14 SRAM & DRAM cells
Phase 15 Register files & the memory array (build one)
Phase 16 The memory hierarchy & locality (the conceptual capstone)
Phase 17 ISA design: the toy instruction set
Phase 18 Number representation revisited (explain it)
Phase 19 The datapath (build the body)
Phase 20 The control unit (the nervous system)
Phase 21 The single-cycle CPU (build it)
Phase 22 The instruction cycle end-to-end
Phase 23 Multi-cycle & the case for pipelining
Phase 24 Machine code & the toy ISA encoding
Phase 25 Writing an assembler
Phase 26 A first program on the CPU
Phase 27 Memory-mapped I/O & a simple peripheral
Phase 28 Pipelining in depth & hazards
Phase 29 Branch prediction & speculation
Phase 30 Caches
Phase 31 SIMD & data parallelism
Phase 32 Multicore, the roofline model & arithmetic intensity
Phase 33 Buses & interconnect
Phase 34 Interrupts & DMA
Phase 35 GPUs & accelerators
Phase 36 FPGAs & reconfigurable logic (optional synthesis path)
Phase 37 Power, clocking & thermal
Phase 38 Verification: testbenches, formal-lite checks & sign-off
Phase 39 Capstone
Phase 40 Hardening, postmortem & "What's Next"
Phase 41 Portal integration