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Level 2 · M.Sc

MSc Advanced Computer Architecture

Hardware · Live · v0

Doctoral computer architecture — microarchitecture, accelerators, memory systems, and performance research.

Path type

Hardware

Requirements

MSc Theory & Applied Hardware

Enrollment

€19.95

Deadline

Next cohort starts 2027-09-06 (AY 2027/28)

Length

~1 year · 42 phases

Language

English · Español

Content freshness

Curriculum updated 2026-08-22 · content rev 9f060c64

Cortex Credits (CC)

126 CC · 280 CC across all tiers of this programme
What are Cortex Credits?

Syllabus

View the phase syllabus

0. Foundations & tooling
1. What "advanced architecture" means
2. The cycle-accurate simulator & the advanced anchor
3. Quantitative performance: CPI, Amdahl & measurement discipline
4. The classic pipeline, rebuilt rigorously
5. Data hazards & the bypass network
6. Control hazards & branch resolution
7. Structural hazards & resource scheduling
8. Precise exceptions & interrupts in a pipeline
9. Pipeline depth, balancing & the frequency/IPC trade
10. Dynamic scheduling: the scoreboard
11. Tomasulo's algorithm & register renaming
12. The reorder buffer & precise out-of-order completion
13. Superscalar fetch, decode & issue
14. Branch prediction in depth
15. Speculative execution, recovery & its security shadow
16. Memory disambiguation & the load/store queue
17. VLIW & the static-vs-dynamic ILP contrast
18. The quantitative cache model
19. Multi-level caches & inclusion
20. Advanced replacement & prefetching
21. Virtual memory, TLBs & page tables
22. Memory consistency models
23. Cache coherence: snooping (MSI/MESI/MOESI)
24. Directory-based coherence
25. Synchronization & memory fences
26. Non-blocking caches, MSHRs & memory-level parallelism
27. Multicore organization & the on-chip interconnect
28. Simultaneous multithreading (SMT)
29. SIMD & vector architectures in depth
30. GPU / SIMT microarchitecture
31. Networks-on-chip: topology & routing
32. The roofline model & performance analysis
33. Domain-specific accelerators & systolic arrays
34. Dataflow & spatial architectures
35. Static timing analysis & critical-path closure
36. Clock distribution, CDC & metastability (rigorous)
37. Power, energy & DVFS
38. Low-power microarchitecture
39. Reliability: soft errors, ECC & RAS
40. Variability, aging & process corners
41. Asynchronous & GALS design

Syllabus →

Enrolment prerequisites

• A verified account and admissions-committee approval.
• Recommended path: MSc Theory & Applied Hardware (advisory, not blocking).