Level 2 · M.Sc

Advanced Computer Architecture

MSc syllabus · 42 phases · ~1 year

Every unit this programme teaches, in the order it is taught. Headlines only — the material itself opens once you are enrolled.

Dates, price and prerequisites

Phase 0 Foundations & tooling
Phase 1 What "advanced architecture" means
Phase 2 The cycle-accurate simulator & the advanced anchor
Phase 3 Quantitative performance: CPI, Amdahl & measurement discipline
Phase 4 The classic pipeline, rebuilt rigorously
Phase 5 Data hazards & the bypass network
Phase 6 Control hazards & branch resolution
Phase 7 Structural hazards & resource scheduling
Phase 8 Precise exceptions & interrupts in a pipeline
Phase 9 Pipeline depth, balancing & the frequency/IPC trade
Phase 10 Dynamic scheduling: the scoreboard
Phase 11 Tomasulo's algorithm & register renaming
Phase 12 The reorder buffer & precise out-of-order completion
Phase 13 Superscalar fetch, decode & issue
Phase 14 Branch prediction in depth
Phase 15 Speculative execution, recovery & its security shadow
Phase 16 Memory disambiguation & the load/store queue
Phase 17 VLIW & the static-vs-dynamic ILP contrast
Phase 18 The quantitative cache model
Phase 19 Multi-level caches & inclusion
Phase 20 Advanced replacement & prefetching
Phase 21 Virtual memory, TLBs & page tables
Phase 22 Memory consistency models
Phase 23 Cache coherence: snooping (MSI/MESI/MOESI)
Phase 24 Directory-based coherence
Phase 25 Synchronization & memory fences
Phase 26 Non-blocking caches, MSHRs & memory-level parallelism
Phase 27 Multicore organization & the on-chip interconnect
Phase 28 Simultaneous multithreading (SMT)
Phase 29 SIMD & vector architectures in depth
Phase 30 GPU / SIMT microarchitecture
Phase 31 Networks-on-chip: topology & routing
Phase 32 The roofline model & performance analysis
Phase 33 Domain-specific accelerators & systolic arrays
Phase 34 Dataflow & spatial architectures
Phase 35 Static timing analysis & critical-path closure
Phase 36 Clock distribution, CDC & metastability (rigorous)
Phase 37 Power, energy & DVFS
Phase 38 Low-power microarchitecture
Phase 39 Reliability: soft errors, ECC & RAS
Phase 40 Variability, aging & process corners
Phase 41 Asynchronous & GALS design