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Level 3 · Ph.D

Advanced Computer Architecture

Ph.D syllabus · 56 phases · +1 year

Every unit this programme teaches, in the order it is taught. Headlines only — the material itself opens once you are enrolled.

Dates, price and prerequisites

1. Phase 0 Foundations & tooling
2. Phase 1 What "advanced architecture" means
3. Phase 2 The cycle-accurate simulator & the advanced anchor
4. Phase 3 Quantitative performance: CPI, Amdahl & measurement discipline
5. Phase 4 The classic pipeline, rebuilt rigorously
6. Phase 5 Data hazards & the bypass network
7. Phase 6 Control hazards & branch resolution
8. Phase 7 Structural hazards & resource scheduling
9. Phase 8 Precise exceptions & interrupts in a pipeline
10. Phase 9 Pipeline depth, balancing & the frequency/IPC trade
11. Phase 10 Dynamic scheduling: the scoreboard
12. Phase 11 Tomasulo's algorithm & register renaming
13. Phase 12 The reorder buffer & precise out-of-order completion
14. Phase 13 Superscalar fetch, decode & issue
15. Phase 14 Branch prediction in depth
16. Phase 15 Speculative execution, recovery & its security shadow
17. Phase 16 Memory disambiguation & the load/store queue
18. Phase 17 VLIW & the static-vs-dynamic ILP contrast
19. Phase 18 The quantitative cache model
20. Phase 19 Multi-level caches & inclusion
21. Phase 20 Advanced replacement & prefetching
22. Phase 21 Virtual memory, TLBs & page tables
23. Phase 22 Memory consistency models
24. Phase 23 Cache coherence: snooping (MSI/MESI/MOESI)
25. Phase 24 Directory-based coherence
26. Phase 25 Synchronization & memory fences
27. Phase 26 Non-blocking caches, MSHRs & memory-level parallelism
28. Phase 27 Multicore organization & the on-chip interconnect
29. Phase 28 Simultaneous multithreading (SMT)
30. Phase 29 SIMD & vector architectures in depth
31. Phase 30 GPU / SIMT microarchitecture
32. Phase 31 Networks-on-chip: topology & routing
33. Phase 32 The roofline model & performance analysis
34. Phase 33 Domain-specific accelerators & systolic arrays
35. Phase 34 Dataflow & spatial architectures
36. Phase 35 Static timing analysis & critical-path closure
37. Phase 36 Clock distribution, CDC & metastability (rigorous)
38. Phase 37 Power, energy & DVFS
39. Phase 38 Low-power microarchitecture
40. Phase 39 Reliability: soft errors, ECC & RAS
41. Phase 40 Variability, aging & process corners
42. Phase 41 Asynchronous & GALS design
43. Phase 42 Advanced verification: constrained-random & coverage
44. Phase 43 Assertion-based verification
45. Phase 44 Formal verification: model & equivalence checking
46. Phase 45 Performance verification & validation
47. Phase 46 RTL-to-gates: logic synthesis, retiming & mapping
48. Phase 47 Place-and-route & physical-design intuition
49. Phase 48 The FPGA realization path (optional, runtime-gated)
50. Phase 49 Emerging memory & near-data computing
51. Phase 50 Accelerators for ML inference
52. Phase 51 Security architecture
53. Phase 52 The research method & reading the frontier
54. Phase 53 The advanced capstone
55. Phase 54 Hardening, postmortem & adversarial review
56. Phase 55 Portal integration (slug lynx-cortex-advanced-hardware)