Level 3 · Ph.D
Ph.D Advanced Computer Architecture
Hardware · Live · v0
Doctoral computer architecture — microarchitecture, accelerators, memory systems, and performance research.
- Path type
- Hardware
- Requirements
- MSc Advanced Computer Architecture
- Enrollment
-
€19.95
- Deadline
- Next cohort starts 2027-09-06 (AY 2027/28)
- Length
- +1 year · 56 phases
- Language
- English · Español
- Content freshness
- Curriculum updated 2026-08-22 · content rev 9f060c64
- Cortex Credits (CC)
-
280 CC
What are Cortex Credits? - Syllabus
-
View the phase syllabus
- Foundations & tooling
- What "advanced architecture" means
- The cycle-accurate simulator & the advanced anchor
- Quantitative performance: CPI, Amdahl & measurement discipline
- The classic pipeline, rebuilt rigorously
- Data hazards & the bypass network
- Control hazards & branch resolution
- Structural hazards & resource scheduling
- Precise exceptions & interrupts in a pipeline
- Pipeline depth, balancing & the frequency/IPC trade
- Dynamic scheduling: the scoreboard
- Tomasulo's algorithm & register renaming
- The reorder buffer & precise out-of-order completion
- Superscalar fetch, decode & issue
- Branch prediction in depth
- Speculative execution, recovery & its security shadow
- Memory disambiguation & the load/store queue
- VLIW & the static-vs-dynamic ILP contrast
- The quantitative cache model
- Multi-level caches & inclusion
- Advanced replacement & prefetching
- Virtual memory, TLBs & page tables
- Memory consistency models
- Cache coherence: snooping (MSI/MESI/MOESI)
- Directory-based coherence
- Synchronization & memory fences
- Non-blocking caches, MSHRs & memory-level parallelism
- Multicore organization & the on-chip interconnect
- Simultaneous multithreading (SMT)
- SIMD & vector architectures in depth
- GPU / SIMT microarchitecture
- Networks-on-chip: topology & routing
- The roofline model & performance analysis
- Domain-specific accelerators & systolic arrays
- Dataflow & spatial architectures
- Static timing analysis & critical-path closure
- Clock distribution, CDC & metastability (rigorous)
- Power, energy & DVFS
- Low-power microarchitecture
- Reliability: soft errors, ECC & RAS
- Variability, aging & process corners
- Asynchronous & GALS design
- Advanced verification: constrained-random & coverage
- Assertion-based verification
- Formal verification: model & equivalence checking
- Performance verification & validation
- RTL-to-gates: logic synthesis, retiming & mapping
- Place-and-route & physical-design intuition
- The FPGA realization path (optional, runtime-gated)
- Emerging memory & near-data computing
- Accelerators for ML inference
- Security architecture
- The research method & reading the frontier
- The advanced capstone
- Hardening, postmortem & adversarial review
- Portal integration (slug Advanced Computer Architecture)
- Enrolment prerequisites
-
- A verified account and admissions-committee approval.
- Completion of MSc Advanced Computer Architecture.
What changed
Every release of this programme, newest first.
- v0 Pilot Wave A backfill: v0 pilot baseline
Professor: Vacancy available
Sign in to request enrolment