← Back to catalogue

Discipline herald — Hardware
Discipline herald

Level 3 · Ph.D

Ph.D Advanced Computer Architecture

Hardware · Live · v0

Doctoral computer architecture — microarchitecture, accelerators, memory systems, and performance research.

Path type
Hardware
Enrollment

€19.95

Deadline
Next cohort starts 2027-09-06 (AY 2027/28)
Length
+1 year · 56 phases
Language
English · Español
Content freshness
Curriculum updated 2026-08-22 · content rev 9f060c64
Cortex Credits (CC)
280 CC
What are Cortex Credits?
Syllabus
View the phase syllabus
  1. Foundations & tooling
  2. What "advanced architecture" means
  3. The cycle-accurate simulator & the advanced anchor
  4. Quantitative performance: CPI, Amdahl & measurement discipline
  5. The classic pipeline, rebuilt rigorously
  6. Data hazards & the bypass network
  7. Control hazards & branch resolution
  8. Structural hazards & resource scheduling
  9. Precise exceptions & interrupts in a pipeline
  10. Pipeline depth, balancing & the frequency/IPC trade
  11. Dynamic scheduling: the scoreboard
  12. Tomasulo's algorithm & register renaming
  13. The reorder buffer & precise out-of-order completion
  14. Superscalar fetch, decode & issue
  15. Branch prediction in depth
  16. Speculative execution, recovery & its security shadow
  17. Memory disambiguation & the load/store queue
  18. VLIW & the static-vs-dynamic ILP contrast
  19. The quantitative cache model
  20. Multi-level caches & inclusion
  21. Advanced replacement & prefetching
  22. Virtual memory, TLBs & page tables
  23. Memory consistency models
  24. Cache coherence: snooping (MSI/MESI/MOESI)
  25. Directory-based coherence
  26. Synchronization & memory fences
  27. Non-blocking caches, MSHRs & memory-level parallelism
  28. Multicore organization & the on-chip interconnect
  29. Simultaneous multithreading (SMT)
  30. SIMD & vector architectures in depth
  31. GPU / SIMT microarchitecture
  32. Networks-on-chip: topology & routing
  33. The roofline model & performance analysis
  34. Domain-specific accelerators & systolic arrays
  35. Dataflow & spatial architectures
  36. Static timing analysis & critical-path closure
  37. Clock distribution, CDC & metastability (rigorous)
  38. Power, energy & DVFS
  39. Low-power microarchitecture
  40. Reliability: soft errors, ECC & RAS
  41. Variability, aging & process corners
  42. Asynchronous & GALS design
  43. Advanced verification: constrained-random & coverage
  44. Assertion-based verification
  45. Formal verification: model & equivalence checking
  46. Performance verification & validation
  47. RTL-to-gates: logic synthesis, retiming & mapping
  48. Place-and-route & physical-design intuition
  49. The FPGA realization path (optional, runtime-gated)
  50. Emerging memory & near-data computing
  51. Accelerators for ML inference
  52. Security architecture
  53. The research method & reading the frontier
  54. The advanced capstone
  55. Hardening, postmortem & adversarial review
  56. Portal integration (slug Advanced Computer Architecture)
Enrolment prerequisites

What changed

Every release of this programme, newest first.

  1. v0 Pilot Wave A backfill: v0 pilot baseline

Professor: Vacancy available

Sign in to request enrolment

↑↓ to move · ↵ to open · esc to close Sign in to search programmes and course content.